Memory circuits used for data storage and computing operations are used in a large variety of consumer electronics, such as computers and cellular telephones. Memory cells in a memory circuit, such as a static random access memory (SRAM), are typically arranged in an array. This memory array includes individually addressable rows and columns to which data can be written and read. The memory array is considered to be in activation mode when data is transferred to and from the memory array. When the memory array is not accessed and there is no data transfer for a period of time, the memory array can be put in standby mode. A portion of peripheral circuitry will be in power down mode to save power and the array is ready to be accessed with minimum data delay penalty. The memory array can also be put in a sleep mode when the majority of peripheral circuitry is in power down mode or when power is cut off from the circuit. Power is only applied to essential circuits for maintaining the memory cell data.
During all modes of operation the memory array consumes power through memory cell leakages. The leakage power in a present high-performance microprocessor device can reach up to 40% of the total power consumption and the memory cell leakage is a major part of this leakage power. There is an increasing demand in consumer electronic markets for smaller circuit packages that consume less power for the purpose of conserving battery-life, such as wireless communication applications. To achieve reduced power consumption, multiple voltage supplies are used to apply a lower voltage level across the memory array, while using a higher voltage supply for the peripheral. The device performance is maintained while memory array leakage power is reduced. Furthermore, the memory array supply voltage can be further reduced to minimize leakage during standby or sleep mode.
The reduced memory array voltage technique for low leakage designs has a serious effect on the ability of data memory cell to retain data. The stability of the memory cells can be compromised, which means memory array data can be destroyed by read or write operations to the array during the active mode. The memory cells can also lose data during any other operations besides active mode, such as in the standby or sleep mode. FIG. 1 shows a conventional memory array architecture generally designated 10 used in modern SRAM designs for low leakage SRAMs. This design uses two preset voltage regulators 130 and 140 for providing voltage supplies to the memory array 100. Since the array voltage is preset, loss of data can be induced by incorrect voltage levels applied across the memory cells. Also they are not optimum for maintaining stability during internal or external disturbance events. The cause of a disturbance can come from any means such as, process variations, voltage fluctuations, temperature variations, or design flaws. What is needed in the art is design method that minimizes leakage power consumption and sustains memory stability during all modes of operation and disturbances, but dynamically maintains an optimum voltage supply across the memory cell array